Memory layout for reduced line loading

ABSTRACT

Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. patent application Ser. No.16/156,026, filed on Oct. 10, 2018, which claims the benefit of U.S.Provisional Application No. 62/673,233, filed on May 18, 2018. Thecontents of the above-referenced Patent Applications are herebyincorporated by reference in their entirety.

BACKGROUND

Many modern day electronic devices include non-volatile memory.Non-volatile memory is electronic memory that is able to store data inthe absence of power. Some promising candidates for the next generationof non-volatile memory include resistive random-access memory (RRAM).RRAM has a relatively simple structure and is compatible withcomplementary metal-oxide-semiconductor (CMOS) logic fabricationprocesses.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 illustrates a block diagram of some embodiments of a memorydevice with a layout for reduced line loading.

FIGS. 2A-2H illustrate block diagrams of various embodiments of thememory device of FIG. 1 with different conductive-bridge configurations.

FIGS. 3A and 3B illustrate block diagrams of various embodiments of bitcells in the memory device of any one of FIGS. 1 and 2A-2G.

FIGS. 4A and 4B illustrate block diagrams of various embodiments of thememory device of FIG. 1 respectively with the bit cells of FIGS. 3A and3B.

FIGS. 5A-5C illustrate various top layouts of some embodiments of amemory device portion of FIG. 4B.

FIG. 6 illustrates a top layout of some alternative embodiments of thememory device portion of FIG. 5B in which conductive bridges have atwo-row pitch.

FIGS. 7A-7C illustrate various cross-sectional views of some embodimentsof the memory device portion of FIGS. 5A-5C.

FIGS. 8-12 illustrate a series of cross-sectional views of someembodiments of a method for forming a memory device with a layout forreduced line loading.

FIG. 13 illustrates a flowchart of some embodiments of the method ofFIGS. 8-12 .

DETAILED DESCRIPTION

The present disclosure provides many different embodiments, or examples,for implementing different features of this disclosure. Specificexamples of components and arrangements are described below to simplifythe present disclosure. These are, of course, merely examples and arenot intended to be limiting. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

A resistive random-access memory (RRAM) memory device comprises one ormore banks of bit cells, where each bank comprises a plurality of bitcells. The bit cells are arranged in a plurality of rows and a pluralityof columns, and each comprises an access transistor and a RRAMstructure. The RRAM structure comprises a top electrode, a bottomelectrode, and a metal oxide element sandwiched between the top andbottom electrodes. The metal oxide element has a variable resistancerepresenting a bit of data. For example, a low resistance state of themetal oxide element may represent a binary “1”, whereas a highresistance state of the metal oxide element may represent a binary “0”.By applying a set voltage from the top electrode to the bottomelectrode, the metal oxide element may be changed to the low resistancestate. By applying a reset voltage from the top electrode to the bottomelectrode, the metal oxide element may be changed to the high resistancestate. The access transistor is electrically coupled in series with theRRAM structure via the bottom electrode.

Each bank of bit cells further comprises a plurality of word lines, aplurality of bit lines, and a plurality of source lines. The word lineseach extend along a corresponding row and electrically couple with gateelectrodes of access transistors in the corresponding row. The bit lineseach extend along a corresponding column and electrically couple withtop electrodes of RRAM structures in the corresponding column. Thesource lines each extend along a corresponding column and selectivelyelectrically couple with bottom electrodes of RRAM structures in thecorresponding column via access transistors in the corresponding column.The word lines allow access to the bit cells on a row-by-row basis,whereas the source and bit lines allow data to be written to or readfrom accessed bit cells on a column-by-column basis.

A bank of bit cells often has between 128 rows and 512 rows. However,this leads to long source and bit lines, whereby the source and bitlines have high loads. The high loads may, in turn, lead to high minimumread voltages and high minimum write voltages on the source and bitlines. Read voltages and write voltages below the high minimum readvoltages and the high minimum write voltages lead to instability whilereading from and writing to the bit cells. Further, the high minimumread voltages and the high minimum write voltages may, in turn, lead tohigh dynamic power consumption. One solution to mitigate the effects oflong source and bit lines is to use smaller banks of bit cells. Forexample, one large bank of bit cells with 128 rows may be replaced withtwo small banks of bit cells each with 64 rows. However, increasing thenumber of banks of bit cells increases the area used by the bit cells,which may increase costs.

Various embodiments of the present application are directed a memorylayout for reduced line loading. In some embodiments, a memory devicecomprises an array of bit cells, a first conductive line, a secondconductive line, and a plurality of conductive bridges. The first andsecond conductive lines may, for example, be source lines or some otherconductive lines. The array of bit cells comprises a plurality of rowsand a plurality of columns, and the plurality of columns comprise afirst column and a second column. The first conductive line extendsalong the first column and is electrically coupled to bit cells in thefirst column. The second conductive line extends along the second columnand is electrically coupled to bit cells in the second column. Theconductive bridges extend from the first conductive line to the secondconductive line and electrically couple the first and second conductivelines together.

By electrically coupling the first and second conductive lines together,the first and second conductive lines define a composite line with aneffective width greater than (e.g., about double) individual widths ofthe first or second conductive lines. The increased width, in turn,reduces resistance and loading along the composite line, such that thevoltage drop along the composite line is low. As a result of the lowvoltage drop, the minimum read and write voltages are low and dynamicpower consumption is low. Further, the memory device may have a singlelarge bank of bit cells, instead of multiple small banks of bit cells,whereby memory density may be high and costs may be low.

With reference to FIG. 1 , a block diagram 100 of some embodiments of amemory device with a memory layout for reduced line loading is provided.The memory device may, for example, be an RRAM memory device, amagnetoresistive random-access memory (MRAM) memory device, aferroelectric random-access memory (FeRAM), or some other suitable typeof memory device. The memory device comprises a plurality of bit cells102. For ease of illustration, only some of the bit cells 102 arelabeled 102.

The bit cells 102 are in M columns and N rows to define an array 104,where M and N are integers greater than zero. For clarity, the columnsare labeled C₁ to C_(M) and the rows are labeled R₁ to R_(N>).Additionally, the bit cells 102 have internal data states representingbits of data. In some embodiments in which the memory device is an RRAMmemory device, the bit cells 102 have individual metal oxide elementswith variable resistances that define the internal data states. Forexample, a low resistance state of a metal oxide element may represent abinary “1”, and a high resistance state of a metal oxide element mayrepresent a binary “0”, or vice versa. The bit cells 102 may, forexample, be one-transistor two-resistor (1T1R) bit cells, two-transistorone-resistor (2T1R) bit cells, one-transistor one-capacitor (1T1C) bitcells, two-transistor one-capacitor (2T1C) bit cells, or some othersuitable type of bit cell.

A set of word lines (not shown) facilitate selection of the bit cells102 on a row-by-row basis, whereas a set of bit lines 106 and a set ofsource lines 108 facilitate reading from and/or writing to selected bitcells on a column-by-column basis. For ease of illustration, only someof the bit lines 106 are labeled 106 and only some of the source lines108 are labeled 108. The bit lines 106 extend laterally alongcorresponding columns of the array 104, from a first side of the array104 to a second side of the array 104 that is opposite the first side.Further, the bit lines 106 electrically couple with bit cells in thecorresponding columns. For clarity, the bit lines 106 are labeled BL₁ toBL_(M), where M is the number of columns (see above). In someembodiments, the bit lines 106 correspond to the columns with aone-to-one correspondence. For example, bit line BL₁ may correspond tocolumn C₁, bit line BL₂ may correspond to column C₂, bit line BL₃ maycorrespond to column C₃, and so on.

The columns of the array 104 are grouped into pairs of neighboringcolumns, and the source lines 108 extend laterally along correspondingpairs of neighboring columns, from the first side of the array 104 tothe second side of the array 104. Further, the source lines 108electrically couple with bit cells in the corresponding pairs ofneighboring columns. For clarity, the source lines 108 are labeled SL₁to SL_(X), where X is an integer representing the number of pairs ofneighboring columns. In some embodiments, the source lines 108correspond to the neighboring pairs of columns with a one-to-onecorrespondence. For example, column C₁ and column C₂ may be paired andmay correspond to source line SL₁, column C₃ and column C₄ may be pairedand may correspond to source line SL₂, and so on.

A plurality of conductive bridges 110 interconnect the source lines 108to reduce line loading on the source lines 108. The conductive bridges110 are spaced along the columns and each electrically couple two ormore source lines together. By electrically coupling two source linestogether, the two source lines define a composite source line with aneffective width greater than (e.g., about double) individual widths ofthe two source lines. The increased width, in turn, reduces resistanceand loading along the composite source line, such that the voltage dropalong the composite source line is low. As a result of the low voltagedrop, the minimum read and write voltages are low and dynamic powerconsumption is low. Further, the memory device may have a single largebank of bit cells, instead of multiple small banks of bit cells, wherebymemory density may be high and costs may be low.

In some embodiments, the conductive bridges 110 are evenly spaced alongthe columns and/or are laterally elongated in parallel. In someembodiments, the conductive bridges 110 are laterally elongatedperpendicular and/or transverse to the source lines 108. In someembodiments, the source lines 108 are grouped into pairs of neighboringsource lines and the conductive bridges 110 electrically couple and/orelectrically short the neighboring source lines in each pair. Forexample, source line SL₁ and source line SL₂ may be paired andelectrically coupled together. In some embodiments, the conductivebridges 110 are integrated and/or continuous with the source lines 108.In some embodiments, the conductive bridges 110 are or comprise copper,aluminum copper, aluminum, some other suitable metal, some othersuitable conductive material(s), or any combination of the foregoing.

In some embodiments, the conductive bridges 110, the source lines 108,the bit lines 106, or any combination of the foregoing are defined bymetal layers of a back-end-of-line (BEOL) interconnect structure. Forexample, the conductive bridges 110 and the source lines 108 may bedefined in metal 1 of a BEOL interconnect structure, and/or the bitlines 106 may be defined in metal 3 or 4 of the BEOL interconnectedstructure.

With reference to FIGS. 2A-2H, block diagrams 200A-200H of variousembodiments of the memory device of FIG. 1 are provided with differentconfigurations for the conductive bridges 110. FIGS. 2A-2F illustratethe memory device with at least 6 rows and at least 12 columns, whereasFIGS. 2G and 2H illustrate the memory device with at least 4 rows and atleast 8 columns. However, these sizes should not be construed aslimiting. FIGS. 2A-2F may have more or less rows and/or more or lesscolumns in other embodiments. Similarly, FIGS. 2G and 2H may have moreor less rows and/or more or less columns in other embodiments.

As illustrated by the block diagram 200A of FIG. 2A, the source lines108 are grouped into neighboring pairs, which are non-overlapping. Forexample, source line SL₁ and source SL₂ may be grouped into aneighboring pair. Further, the conductive bridges 110 each correspond toone of the neighboring pairs of source lines and each electricallycouples source lines in the corresponding neighboring pair. In someembodiments, the correspondence between the conductive bridges 110 andthe neighboring pairs is many-to-one.

Also illustrated by the block diagram 200A of FIG. 2A, the conductivebridges 110 are evenly spaced along the columns and have a one-rowpitch. Therefore, two conductive bridges neighboring in the same columnmay, for example, be separated by a single row of bit cells.

As illustrated by the block diagram 200B of FIG. 2B, a variant of FIG.2A is provided in which the conductive bridges 110 have a two-row pitch.Therefore, two conductive bridges neighboring in the same column may,for example, be separated by two rows of bit cells.

As illustrated by the block diagram 200C of FIG. 2C, a variant of FIG.2A is provided in which the conductive bridges 110 have a three-rowpitch. Therefore, two conductive bridges neighboring in the same columnmay, for example, be separated by three rows of bit cells.Notwithstanding that FIGS. 2A-2C illustrate the conductive bridges 110with pitches of one, two, and three rows, other pitches are amenable.

As illustrated by the block diagram 200D of FIG. 2D, the source lines108 are grouped into groups of three, where the groups arenon-overlapping and each group comprises three neighboring source lines.For example, source line SL₁, source SL₂, and source SL₃ may be grouped.Further, the conductive bridges 110 each correspond to one of the groupsand each electrically couples source lines in the corresponding group.In some embodiments, the correspondence between the conductive bridges110 and the groups is many-to-one.

Also illustrated by the block diagram 200D of FIG. 2D, the conductivebridges 110 are evenly spaced along the columns and have a one-rowpitch.

As illustrated by the block diagram 200E of FIG. 2E, a variant of FIG.2D is provided in which the conductive bridges 110 have a two-row pitch.Notwithstanding that FIGS. 2D and 2E illustrate the conductive bridges110 with pitches of one and two rows, three-row pitches, four-rowpitches, and other pitches are amenable.

As illustrated by the block diagram 200F of FIG. 2F, the source lines108 are grouped into groups of three, where the groups arenon-overlapping and each group comprises three neighboring source lines.For example, source line SL₁, source SL₂, and source SL₃ may be grouped.Further, the conductive bridges 110 each correspond to one of the groupsand each electrically couples two source lines in the correspondinggroup. At each of the groups, the conductive bridges for the groupalternate between electrically coupling the first two source lines ofthe group and the second two source lines of the group. For example, ata group made up of source line SL₁, source SL₂, and source SL₃, theconductive bridges corresponding to the group may alternate betweenelectrically coupling source line SL₁ and source line SL₂ andelectrically coupling source line SL₂ and source line SL₃. In someembodiments, the correspondence between the conductive bridges 110 andthe groups is many-to-one.

Also illustrated by the block diagram 200F of FIG. 2F, the conductivebridges 110 are evenly spaced, albeit staggered, along the columns andhave a one-row pitch. Notwithstanding that FIG. 2F illustrates theconductive bridges 110 with a one-row pitch, two-row pitches, three-rowpitches, and other pitches are amenable.

As illustrated by the block diagram 200G of FIG. 2G, the source lines108 are grouped into pairs, such that the pairs are non-overlapping andthe source lines of each pair are separated by a single source line. Forexample, source line SL₁ and source line SL₃ may be paired since sourcelines SL₁, SL₃ are separated by source line SL₂. As another example,source line SL₂ and source line SL₄ may be paired since source linesSL₂, SL₄ are separated by source line SL₃. Further, the conductivebridges 110 each corresponds to one of the pairs of source lines andeach electrically couples source lines in the corresponding neighboringpair. In some embodiments, the correspondence between the conductivebridges 110 and the pairs is many-to-one.

Also illustrated by the block diagram 200G of FIG. 2G, the conductivebridges 110 are evenly spaced within corresponding columns by a one-rowpitch. Notwithstanding that FIG. 2G illustrates the conductive bridges110 with a one-row pitch, two-row pitches, three-row pitches, and otherpitches are amenable.

As illustrated by the block diagram 200H of FIG. 2H, the source lines108 are grouped into groups of four, where the groups arenon-overlapping and each group comprises four neighboring source lines.For example, source line SL₁, source line SL₂, source line SL₃, andsource line SL₄ may be grouped. Note that only one group has beenillustrated. Further, the conductive bridges 110 each correspond to oneof the groups and each electrically couples two source lines in thecorresponding group. At each of the groups, the conductive bridges forthe group alternate between electrically coupling the first and thirdsource lines of the group and the second and fourth source lines of thegroup. For example, at a group made up of source line SL₁, source lineSL₂, source line SL₃, and source line SL₄, conductive bridges in thegroup may alternate between electrically coupling source line SL₁ andsource line SL₃ and electrically coupling source line SL₂ and sourceline SL₄. In some embodiments, the correspondence between the conductivebridges 110 and the groups is many-to-one.

Also illustrated by the block diagram 200H of FIG. 2H, the conductivebridges 110 are evenly spaced, albeit staggered, along the columns andhave a one-row pitch. Notwithstanding that FIG. 2H illustrates theconductive bridges 110 with a one-row pitch, two-row pitches, three-rowpitches, and other pitches are amenable.

With reference to FIG. 3A, a block diagram 300A of some embodiments of abit cell 102 in any one of FIGS. 1 and 2A-2H is provided. The bit cell102 comprises a memory structure 302 and an access transistor 304. Thememory structure 302 and the access transistor 304 are electricallycoupled in series from a bit line BL to a source line SL, and the accesstransistor 304 is gated by a word line WL. The memory structure 302 isconfigured to store a bit of data and may, for example, be an RRAMstructure, an MRAM structure, or some other suitable memory structure.The access transistor 304 may, for example, be ametal-oxide-semiconductor field-effect transistor (MOSFET), some othersuitable insulated-gate field-effect transistor (IGFET), or some othersuitable transistor.

With reference to FIG. 3B, a block diagram 300B of some alternativeembodiments of the bit cell 102 of FIG. 3A is provided in which the bitcell 102 further comprises a second access transistor 306. The accesstransistor 304 (also known as the first access transistor 304) and thesecond access transistor 306 are electrically coupled in parallel fromthe memory structure 302 to the source line SL. Further, the first andsecond access transistors 304, 306 are respectively gated by the wordline WL (also known as the first word line WL) and a second word lineWL′. The second access transistor 306 may, for example, be a MOSFET, anIGFET, or some other suitable transistor.

With reference to FIGS. 4A and 4B, block diagrams 400A, 400B of variousembodiments of the memory device of FIG. 1 are provided respectivelywith embodiments of the bit cell 102 in FIGS. 3A and 3B. Also note thatrow R₃ is not specifically shown in FIGS. 4A and 4B to improve thecompactness of FIGS. 4A and 4B.

As illustrated by the block diagram 400A of FIG. 4A, each of the bitcells 102 is as illustrated and described with regard to FIG. 3A. Forease of illustration, only some of the bit cells 102 are labeled 102.Further, the memory structure 302 and the access transistor 304 are onlylabeled for some of the bit cells 102.

A set of word lines 402 facilitates selection of the bit cells 102 on arow-by-row basis, whereas the set of bit lines 106 and the set of sourcelines 108 facilitate reading from and/or writing to selected bit cellson a column-by-column basis. For ease of illustration, only some of thebit lines 106 are labeled 106 and only some of the source lines 108 arelabeled 108. The word lines 402 extend laterally along correspondingrows of the array 104. Further, the word lines 402 electrically couplewith bit cells in the corresponding rows. For clarity, the word lines402 are labeled WL₁ to WL_(N), where N is the number of rows. In someembodiments, the word lines 402 correspond to the rows with a one-to-onecorrespondence. For example, word line WL₁ may correspond to row R₁,word line WL₂ may correspond to row R₂, and so on.

As illustrated by the block diagram 400B of FIG. 4B, a variant of FIG.4A is provided in which each of the bit cells 102 is as illustrated anddescribed with regard to FIG. 3B. For ease of illustration, the memorystructure 302, the first access transistor 304, and the second accesstransistor 306 are only labeled for some of the bit cells 102.

The set of word lines 402 (also known as the set of first word lines402) and a set of second word lines 404 facilitate selection of the bitcells 102 on a row-by-row basis. The second word lines 404 extendlaterally along corresponding rows of the array 104. Further, the secondword lines 404 electrically couple with bit cells in the correspondingrows. For clarity, the second word lines 404 are labeled WL′₁ toWL′_(N), where N is the number of rows. In some embodiments, the secondword lines 404 correspond to the rows with a one-to-one correspondence.For example, second word line WL′₁ may correspond to row R₁, second wordline WL′2 may correspond to row R₂, and so on.

While FIGS. 4A and 4B illustrate bit cell embodiments in FIGS. 3A and 3Busing the memory device of FIG. 1 , it is to be appreciated that the bitcell embodiments may be used in any one of FIGS. 2A-2G in otherembodiments. For example, each of the bit cells 102 in FIG. 2A may be asillustrated with regard to FIG. 3A or FIG. 3B. As another example, eachof the bit cells 102 in FIG. 2E may be as illustrated with regard toFIG. 3A or FIG. 3B.

With reference to FIGS. 5A-5C, various top layouts 500A-500C of someembodiments of a memory device portion of FIG. 4B is provided. The toplayouts 500A-500C may, for example, be taken within box BX in FIG. 4B,but other locations are amenable. The top layout 500A of FIG. 5A islimited to features in the front end of line (FEOL) and contact vias,such that wires and inter-wire vias are not shown. The top layouts 500B,500C of FIGS. 5B and 5C include the features of FIG. 5A, and furtherinclude wires in the BEOL.

As illustrated by the top layout 500A of FIG. 5A, the bit cells 102 arerespectively on device regions 502 d of a semiconductor substrate 502.For ease of illustration, only some of the bit cells 102 are identified.The device regions 502 d accommodate source/drain regions (not shown) ofthe first and second access transistors 304, 306 in FIG. 4B and areseparated and demarcated by isolation structures 504. The device regions502 d and the isolation structures 504 extend laterally in a Ydirection. The Y direction may, for example, correspond to columns inthe array 104 of bit cells. See, for example, columns C₁-C₄ in FIG. 4B.In some embodiments, the device regions 502 d and the isolationstructures 504 are line shaped and/or are substantially parallel to eachother. Other shapes are, however, amenable. The semiconductor substrate502 may, for example, be a bulk silicon substrate, some other suitablebulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, orsome other suitable semiconductor substrate. The isolation structures504 may, for example, be shallow trench isolation (STI) structures, deeptrench isolation (DTI) structure, or some other suitable isolationstructure.

The first and second word lines 402, 404 extend laterally in an Xdirection across the device regions 502 d and the isolation structure504. The X direction may, for example, correspond to rows in the array104 of bit cells. See, for example, rows R₁-R_(N) in FIG. 4B. In someembodiments, the first and second word lines 402, 404 are line shapedand/or are substantially parallel to each other. Other shapes are,however, amenable. The first word lines 402 define gate electrodes ofthe first access transistors 304 in FIG. 4B and the second word lines404 define gate electrodes of the second access transistors 306 in FIG.4B. The first and second word lines 402, 404 may, for example, be orcomprise doped polysilicon, metal, some other suitable conductivematerial(s), or any combination of the foregoing.

Contact vias 506 are on the device regions 502 d and electrically couplecomponents of the bit cells 102 to overlying structure when viewed incross section. For ease of illustration, only some of the contact vias506 are labeled 506. Such components may, for example, include the firstaccess transistors 304 (not shown) in FIG. 4B and the second accesstransistors 306 (not shown) in FIG. 4B. The contact vias 506 may, forexample, be or comprise tungsten, some other suitable metal orconductive material(s), or any combination of the foregoing.

As illustrated by the top layout 500B of FIG. 5B, the features of FIG.5A are included along with a plurality of lower-level wires 508. Forease of illustration, only some of the lower-level wires 508 are labeled508. When viewed in cross section, the lower-level wires 508 have acommon elevation above the semiconductor substrate 502 and adjoin orotherwise neighbor the contact vias 506 (see FIG. 5A). For example, thelower-level wires 508 may correspond to metal 1 in a BEOL interconnectstructure. The lower-level wires 508 include a composite source line 508a that comprises the source lines 108 and the conductive bridges 110.The composite source line 508 a has a ladder-shaped layout in which legsof the ladder-shaped layout and rungs of the ladder-shaped layout arerespectively defined by the source lines 108 and the conductive bridges110. Other layouts are, however, amenable in other embodiments.

The source lines 108 extend laterally in the Y direction, respectivelyon the isolation structures 504 (see FIG. 5A), and the conductivebridges 110 extend laterally in the X direction. In some embodiments,the source lines 108 are line shaped and/or are substantially parallelto each other. Similarly, in some embodiments, the conductive bridges110 are line shaped and/or substantially parallel to each other. Othershapes are, however, amenable for the source lines 108 and/or theconductive bridges 110. In some embodiments, the conductive bridges 110are evenly spaced in the Y direction. The source lines 108 electricallycouple to the first and second access transistors 304, 306 (not shown)in FIG. 4B by way of the contact vias 506 (see FIG. 5A).

As discussed above, the conductive bridges 110 each electrically coupletwo or more source lines together to reduce line loading on the sourcelines. By electrically coupling two source lines together, the twosource lines define a composite source line with an effective widthgreater than (e.g., about double) individual widths of the two sourcelines. The increased width, in turn, reduces resistance and loadingalong the composite source line, such that the voltage drop along thecomposite source line is low. As a result of the low voltage drop, theminimum read and write voltages are low and dynamic power consumption islow.

The lower-level wires 508 further include lower-level islands 508 b. Forease of illustration, only some of the lower-level islands 508 b arelabeled 508 b. Similar to the source lines 108, the lower-level islands508 b electrically couple to the first and second access transistors304, 306 (not shown) in FIG. 4B by way of the contact vias 506 (see FIG.5A). As seen hereafter, the lower-level islands 508 b serve as basesupon which to form memory structures (not shown) and through which thememory structures are electrically coupled to the first and secondaccess transistors 304, 306 in FIG. 4B.

As illustrated by the top layout 500C of FIG. 5C, the features of FIG.5B are included along with a plurality of upper-level wires 510. Whenviewed in cross section, the upper-level wires 510 have a commonelevation above the semiconductor substrate 502 and overlie thelower-level wires 508. The upper-level wires 510 may, for example,correspond to metal 3 or metal 4 in a BEOL interconnect structure. Theupper-level wires 510 include the bit lines 106. The bit lines 106respectively overlie and electrically couple to the memory structures302 (not shown) in FIG. 4B when viewed in cross section. Further, thebit lines 106 extend laterally in the Y direction. In some embodiments,the bit lines 106 are line shaped and/or are substantially parallel toeach other. Other shapes are, however, amenable for the bit lines 106.

While the conductive bridges 110 and the source lines 108 areillustrated as being at a common elevation above the semiconductorsubstrate 502 when viewed in cross section, the conductive bridges 110and the source lines 108 may alternatively be at different elevationswhen viewed in cross section. For example, the conductive bridges 110may be at metal 2 of a BEOL interconnect structure, and the source lines108 may be at metal 1 of the BEOL interconnect structure, or vice versa.Further, while the bit cells 102 are illustrated using embodiments inFIG. 3B, the bit cells 102 may alternatively use embodiments in FIG. 3Aby at least removing the second word lines 404. Further, while theconductive bridges 110 are illustrated using a conductive bridgeconfiguration in FIG. 4B, the conductive bridges 110 may alternativelyuse a conductive bridge configuration in any one of FIGS. 1, 2A-2H, and4A.

With reference to FIG. 6 , a top layout 600 of some alternativeembodiments of the memory device portion of FIG. 5B is provided in whichthe conductive bridges 110 have a two-row pitch instead of a one-rowpitch. Therefore, two conductive bridges neighboring in the same columnmay, for example, be separated by two rows of bit cells. Compare FIG. 2A(which has a one-row pitch) to FIG. 2B (which has a two-row pitch).Having a pitch of two-rows or more for the conductive bridges 110relaxes design constraints of the lower-level islands 508 b and allowsthe lower-level islands 508 b to be larger than with a one-row pitch.

With reference to FIGS. 7A-7C, various cross-sectional views 700A-700Cof some embodiments of the memory device portion of FIGS. 5A-5C isprovided. The cross-sectional views 700A-700C may, for example,respectively be taken along lines A-C in FIGS. 5A-5C.

As illustrated by the cross-sectional view 700A of FIG. 7A, a firstaccess transistor 304 and a second access transistor 306 are on asemiconductor substrate 502. The first and second access transistors304, 306 comprise individual source/drain regions 702 i and a sharedsource/drain region 702 s. The individual source/drain regions 702 i andthe shared source/drain region 702 s are in the semiconductor substrate502 and have the same doping type, which is different than the dopingtype of adjoining portions of the semiconductor substrate 502. Further,the shared source/drain region 702 s is between the individualsource/drain regions 702 i.

A first word line 402 and a second word line 404 respectively definegate electrodes of the first access transistor 304 and the second accesstransistor 306. As such, when the first word line 402 is appropriatelybiased, a portion of the semiconductor substrate 502 directly under thefirst word line 402 may conduct from the shared source/drain region 702s to a corresponding one of the individual source/drain regions 702 i.Similarly, when the second word line 404 is appropriately biased, aportion of the semiconductor substrate 502 directly under the secondword line 404 may conduct from the shared source/drain region 702 s to acorresponding one of the individual source/drain regions 702 i. Thefirst and second word lines 402, 404 are spaced from the semiconductorsubstrate 502 by corresponding word line dielectric layers 704 and maybe or comprise, for example, doped polysilicon, metal, some othersuitable conductive material(s), or a combination of the foregoing. Theword line dielectric layers 704 may, for example, be silicon oxideand/or some other suitable dielectric(s).

An interconnect structure 706 overlies the first and second accesstransistors 304, 306. The interconnect structure 706 comprises aninterconnect dielectric layer 708, and further comprises a plurality ofvias and a plurality of wires. The interconnect dielectric layer 708may, for example, be or comprise silicon oxide, a low κ dielectric, someother suitable dielectric(s), or any combination of the foregoing. A lowκ dielectric may be, for example, a dielectric with a dielectricconstant κ less than about 3.9, 3, 2, or 1. The plurality of viascomprises a contact via 506 and an inter-wire via 710. The plurality ofwires comprises a composite source line 508 a, a lower-level island 508b, a mid-level island 712, and a bit line 106.

The composite source line 508 a and the lower-level island 508 b are ata first elevation above the semiconductor substrate 502. The compositesource line 508 a comprises conductive bridges 110 and may, for example,have a ladder-shaped top layout in which rungs of the ladder shape aredefined by the conductive bridges 110. An example of the ladder-shapedtop layout is in FIG. 5B. Notwithstanding that the composite source line508 a may have a ladder-shaped top layout, other top layouts areamenable. The lower-level island 508 b overlies the shared source/drainregion 702 s and is electrically coupled to the shared source/drainregion 702 s by the contact via 506. The mid-level island 712 is at asecond elevation above the semiconductor substrate 502 and the secondelevation is greater than the first elevation. Further, the mid-levelisland 712 overlies the lower-level island 508 b and is electricallycoupled to the lower-level island 508 b by the inter-wire via 710. Thebit line 106 is at a third elevation above the semiconductor substrate502 and the third elevation is greater than the second elevation.

The vias and the wires are alternatingly stacked in the interconnectdielectric layer 708 to define conductive paths. The contact via 506,the inter-wire via 710, the lower-level island 508 b, and the mid-levelisland 712 define a conductive path from the shared source/drain region702 s to a memory structure 302. Further, the bit line 106 defines aconductive path from the memory structure 302 to a periphery the memorydevice. As noted above, the memory structure 302 is configured to storea bit of data and may, for example, be an RRAM structure, an MRAMstructure, or some other suitable memory structure.

As illustrated by the cross-sectional view 700B of FIG. 7B, thecomposite source line 508 a further comprises a source line 108electrically coupled to the individual source/drain regions 702 i byadditional contact vias 506. In embodiments in which the compositesource line 508 a has a ladder-shaped top layout, a leg of the laddershape may be defined by the source line 108. As above, even though thecomposite source line 508 a may have a ladder-shaped top layout, othertop layouts are amenable.

As illustrated by the cross-sectional view 700C of FIG. 7C, the sharedsource/drain region 702 s is sandwiched between a pair of isolationstructures 504. Further, the contact via 506, the lower-level island 508b, the inter-wire via 710, and the mid-level island 712 define aconductive path from the shared source/drain region 702 s to the memorystructure 302.

While the cross-sectional views 700A-700C of FIGS. 7A-7C are illustratedusing embodiments of the memory device in FIG. 4B, it is to beunderstood that the cross-sectional views 700A-700C may be used withother embodiments of the memory device. For example, the cross-sectionalviews 700A-700C may be used with embodiments of the memory device inFIG. 4A by removing second word lines 404 and the second accesstransistors 306.

With reference to FIGS. 8-12 , a series of cross-sectional views800-1200 of some embodiments of a method for forming a memory devicewith a layout for reduced line loading is provided. The method may, forexample, be employed to form the memory device in any one of FIGS. 1,2A-2H, 4A, 4B, 5A-5C, 6, and 7A-7C. However, the method is illustratedusing some embodiments of the memory device in FIG. 7A. Hence, thecross-sectional views 800-1200 may, for example, be taken along line Ain any one of FIGS. 5A-5C. As above, FIGS. 5A-5C may, for example, betaken within box BX in FIG. 4B.

As illustrated by the cross-sectional view 800 of FIG. 8 , a firstaccess transistor 304 and a second access transistor 306 are formed on asemiconductor substrate 502. The first and second access transistors304, 306 comprise individual source/drain regions 702 i and a sharedsource/drain region 702 s. The individual source/drain regions 702 i andthe shared source/drain region 702 s are in the semiconductor substrate502 with the shared source/drain region 702 s between the individualsource/drain regions 702 i. The first and second access transistors 304,306 further comprise gate electrodes and gate dielectric layers. Thegate electrodes are respectively defined by a first word line 402 and asecond word line 404, and the gate dielectric layers are respectivelydefined by word line dielectric layers 704. The word line dielectriclayers 704 each overlie the semiconductor substrate 502, laterallybetween the shared source/drain region 702 s and a respective one of theindividual source/drain regions 702 i. Further, the first and secondword lines 402, 404 respectively overlie the word line dielectric layers704.

In some embodiments, a process for forming the first and second accesstransistors 304, 306 comprises: 1) forming the first and second wordlines 402, 404 and the word line dielectric layers 704 on thesemiconductor substrate 502; and 2) subsequently forming the individualsource/drain regions 702 i and the shared source/drain region 702 s.

In some embodiments, the first and second word lines 402, 404 and theword line dielectric layers 704 comprises: 1) depositing a dielectriclayer covering the semiconductor substrate 502; 2) depositing aconductive layer covering the dielectric layer; and 3) patterning thedielectric layer and the conductive layer respectively into the wordline dielectric layers 704 and the first and second word lines 402, 404.The depositing of the dielectric layer may, for example, be performed bychemical vapor deposition (CVD), physical vapor deposition (PVD),thermal oxidation, some other suitable deposition process(es), or anycombination of the foregoing. The depositing of the conductive layermay, for example, be performed by CVD, PVD, electroless plating,electroplating, some other suitable deposition process, or anycombination of the foregoing. The patterning may, for example, comprisea photolithography/etching process and/or some other suitable patterningprocess(es).

In some embodiments, the forming of the individual source/drain regions702 i and the shared source/drain region 702 s comprises ionimplantation in which dopants are implanted into the semiconductorsubstrate 502 with the first and second word lines 402, 404 in place. Insome embodiments, the first and second word lines 402, 404 or hard masks(not shown) on the first and second word lines 402, 404 serve as a maskduring the ion implantation. In alternative embodiments, some otherdoping process(es) is/are performed to form the individual source/drainregions 702 i and the shared source/drain region 702 s.

As illustrated by the cross-sectional view 900 of FIG. 9 , aninterconnect structure 706 is partially formed on the first and secondaccess transistors 304, 306. The interconnect structure 706 comprises aninterconnect dielectric layer 708, a contact via 506, and a plurality oflower-level wires 508. The interconnect dielectric layer 708 comprisesan interlayer dielectric (ILD) layer 708 ild, and further comprises anintermetal dielectric (IMD) layer 708 imd overlying the ILD layer 708ild. The contact via 506 is in the ILD layer 708 ild and extends throughthe ILD layer 708 ild to the shared source/drain region 702 s. Theplurality of lower-level wires 508 is in the IMD layer 708 imd andcomprises a composite source line 508 a and a lower-level island 508 b.Note that the composite source line 508 a is not fully visible withinthe cross-sectional view 900. For a more complete view, see the toplayout 500B of FIG. 5B.

The lower-level island 508 b overlies the shared source/drain region 702s and is electrically coupled to the shared source/drain region 702 s bythe contact via 506. The composite source line 508 a comprisesconductive bridges 110 and source lines 108 (not shown). The sourcelines 108 are outside the cross-sectional view 900 and are electricallycoupled together by the conductive bridges 110. A first one of thesource lines 108 is electrically coupled to the individual source/drainregions 702 i outside of the cross-sectional view 900 by additionalcontact vias (not shown). See the two contact vias 506 along line B inFIGS. 5A-5C. A second one of the source lines 108 is electricallycoupled to individual source/drain regions (not shown) of another bitcell outside of the cross-sectional view 900 by additional contact vias(not shown). By electrically couples the source lines 108 together, thecomposite source line 508 a has an effective width greater thanindividual widths of the source lines 108, whereby a resistance of thecomposite source line 508 a is less than individual resistances of thesource lines 108. This reduces line loading and improves powerefficiency.

In some embodiments, a process for partially forming the interconnectstructure 706 comprises: 1) depositing the ILD layer 708 ild; 2) formingthe contact via 506 in the ILD layer 708 ild; 3) depositing the IMDlayer 708 imd; and 4) forming the plurality of lower-level wires 508 inthe IMD layer 708 imd. The depositing of the ILD and IMD layers 708 ild,708 imd may, for example, be performed by CVD, PVD, some other suitabledeposition process, or any combination of the foregoing. The forming ofthe contact via 506 and the forming of the lower-level wires 508 may,for example, be performed by a single damascene process or some othersuitable process. The single damascene process comprises: 1) patterninga dielectric layer (e.g., the ILD layer 708 ild or the IMD layer 708imd) to form openings with a layout of conductive features being formed(e.g., the contact via 506 or the plurality of lower-level wires 508);2) depositing a conductive layer filling the openings and covering thedielectric layer; and 3) performing a planarization into the conductivelayer until the dielectric layer is reached. The patterning may, forexample, be performed by a photolithography/etching process or someother suitable patterning process. The depositing of the conductivelayer may, for example, be performed by CVD, PVD, electroless plating,electroplating, some other suitable deposition process, or anycombination of the foregoing. The planarization may, for example, beperformed by a chemical mechanical polish (CMP) or some other suitableplanarization process.

As illustrated by the cross-sectional view 1000 of FIG. 10 , theinterconnect structure 706 is extended to include an additional IMDlayer 708 imd, a mid-level island 712, and an inter-wire via 710. Theadditional IMD layer 708 imd overlies the plurality of lower-level wires508 and accommodates both the mid-level island 712 and the inter-wirevia 710. The mid-level island 712 overlies the lower-level island 508 band is electrically coupled to the lower-level island 508 b by theinter-wire via 710.

In some embodiments, a process for extending the interconnect structure706 comprises: 1) depositing the additional IMD layer 708 imd; 2)patterning the additional IMD layer 708 imd to form openings with alayout for both the mid-level island 712 and the inter-wire via 710; 3)depositing a conductive layer filling the openings and covering theadditional IMD layer 708 imd; and 3) performing a planarization into theconductive layer until the additional IMD layer 708 imd is reached. Thepatterning may, for example, be performed by a series of individualpatterning processes, each being a photolithography/etching process orsome other suitable patterning process. The depositing of the conductivelayer may, for example, be performed by CVD, PVD, electroless plating,electroplating, some other suitable deposition process, or anycombination of the foregoing. The planarization may, for example, beperformed by a CMP or some other suitable planarization process.

While not shown, the extension of the interconnect structure 706 may beomitted in other embodiments, such that the additional IMD layer 708imd, the mid-level island 712, and the inter-wire via 710 are omitted.Further, the extension of the interconnect structure 706 may be repeatedone or more times in other embodiments, such that the additional IMDlayer 708 imd, the mid-level island 712, and the inter-wire via 710 arerepeated one or more times.

As illustrated by the cross-sectional view 1100 of FIG. 11 , a memorystructure 302 is formed on the interconnect structure 706. The memorystructure 302 overlies the shared source/drain region 702 s and iselectrically coupled to the shared source/drain region 702 s by theinterconnect structure 706. The memory structure 302 may, for example,be an RRAM structure, an MRAM structure, or some other suitable memorystructure.

In some embodiments, a process for forming the memory structure 302comprises: 1) performing a series of depositions to form a memory filmcomprising a bottom electrode layer, a data storage layer, and a topelectrode layer; and 2) patterning the memory film into the memorystructure 302. The depositing of the bottom and top electrode layersmay, for example, be performed by CVD, PVD, electroless plating,electroplating, some other suitable deposition process(es), or anycombination of the foregoing. The depositing of the data storage layermay, for example, be performed by CVD, PVD, some other suitabledeposition process(es), or any combination of the foregoing. Thepatterning may, for example, be performed by a photolithography/etchingprocess or some other suitable deposition process(es).

As illustrated by the cross-sectional view 1200 of FIG. 12 , theinterconnect structure 706 is extended around the memory structure 302,whereby an additional IMD layer 708 imd and a bit line 106 are formed.The additional IMD layer 708 imd surrounds the memory structure 302, andthe bit line 106 overlies the additional IMD layer 708 imd. Further, thebit line 106 electrically couples to the memory structure 302.

In some embodiments, a process for extending the interconnect structure706 comprises: 1) depositing the additional IMD layer 708 imd; 2)patterning the additional IMD layer 708 imd with an opening having alayout of the bit line 106; 3) depositing a conductive layer filling theopenings and covering the additional IMD layer 708 imd; and 4)performing a planarization into the conductive layer until thedielectric layer is reached. The patterning may, for example, beperformed by a photolithography/etching process or some other suitablepatterning process. The depositing of the conductive layer may, forexample, be performed by CVD, PVD, electroless plating, electroplating,some other suitable deposition process, or any combination of theforegoing. The planarization may, for example, be performed by a CMP orsome other suitable planarization process.

While the cross-sectional views 800-1200 of FIGS. 8-12 are describedwith reference to the method, it will be appreciated that the structuresshown in FIGS. 8-12 are not limited to the method and may stand alonewithout the method. Additionally, while FIGS. 8-12 are described as aseries of acts, it will be appreciated that these acts are not limitingin that the order of the acts can be altered in other embodiments, andthe methods disclosed are also applicable to other structures. In otherembodiments, some acts that are illustrated and/or described may beomitted in whole or in part.

With reference to FIG. 13 , a flowchart 1300 of some embodiments of themethod of FIGS. 8-12 is provided.

At 1302, an array of access transistors is formed on a substrate, wherethe access transistors are in a plurality of rows and a plurality ofcolumns, and where the columns are grouped into pairs of neighboringcolumns. See, e.g., FIGS. 4B, 5A, and 8 .

At 1304, a plurality of lower-level wires is formed above the substrate,where the lower-level wires have a common elevation above the substrateand comprise a plurality of source lines, a plurality of bridges, and aplurality of islands. See, e.g., FIGS. 4B, 5B, and 9 .

At 1304 a, the forming of the plurality of lower-level wires comprisesforming the plurality of source lines, where each of the source lines isindividual to one of the pairs of neighboring columns and iselectrically coupled to sources of access transistors in the individualone of the pairs.

At 1304 b, the forming of the plurality of lower-level wires comprisesforming the plurality of bridges, where the bridges electrically coupleneighboring source lines together. By electrically coupling neighboringsource lines together, composite source lines form with effective widthsgreater than individual widths of the source lines and further havereduced resistances compared to the source lines. The reducedresistances reduce loading along the composite source lines, reducevoltage drops along the composite source lines, reduce the minimum readand write voltages, and reduce dynamic power consumption. As such, thememory device resulting from the method may have a single large bank ofbit cells, instead of multiple small banks of bit cells, which increasesmemory density and reduces costs.

At 1304 c, the forming of the plurality of lower-level wires comprisesforming the plurality of islands, where each of the islands overlies andis electrically coupled to a drain of an individual one of the accesstransistors.

At 1306, a plurality of memory structures is formed, where the memorystructures respectively overlie and electrically couple to the islands.See, e.g., FIGS. 4B, 10, and 11 .

At 1308, a plurality of upper-level wires is formed above the memorystructures, where the upper-level wires have a common elevation abovethe substrate and comprise a plurality of bit lines, and where the bitlines respectively overlie and electrically couple to the memorystructures. See, e.g., FIGS. 4B, 5C, and 12 .

While the flowchart 1300 of FIG. 13 is illustrated and described hereinas a series of acts or events, it will be appreciated that theillustrated ordering of such acts or events is not to be interpreted ina limiting sense. For example, some acts may occur in different ordersand/or concurrently with other acts or events apart from thoseillustrated and/or described herein. Further, not all illustrated actsmay be required to implement one or more aspects or embodiments of thedescription herein, and one or more of the acts depicted herein may becarried out in one or more separate acts and/or phases.

In some embodiments, the present application provides a memory deviceincluding: an array of bit cells including in a plurality of rows and aplurality of columns, wherein the plurality of columns includes a firstcolumn and a second column; a first conductive line extending along thefirst column, wherein the first conductive line is electrically coupledto bit cells of the array in the first column; a second conductive lineextending along the second column, wherein the second conductive line iselectrically coupled to bit cells of the array in the second column; anda plurality of conductive bridges extending from the first conductiveline to the second conductive line and electrically coupling the firstand second conductive lines together. In some embodiments, the pluralityof columns further includes a third column and a fourth column, whereinthe first conductive line extends along the third column and iselectrically coupled to bit cells of the array in the third column, andwherein the second conductive line extends along the fourth column andis electrically coupled to bit cells of the array in the fourth column.In some embodiments, the conductive bridges are evenly spaced along thefirst column. In some embodiments, the conductive bridges are lineshaped and extend transverse to the first and second conductive lines inparallel. In some embodiments, the plurality of conductive bridgesincludes a first conductive bridge and a second conductive bridge, andwherein the first and second conductive bridges border and are separatedalong the first column by two rows of the array. In some embodiments,the plurality of columns further includes a third column, wherein thememory device further includes a third conductive line that extendsalong the third column and is electrically coupled to bit cells of thearray in the third column, and wherein the conductive bridges extendfrom the first column to the second column and from the second column tothe third column. In some embodiments, the plurality of columns furtherincludes a third column, wherein the conductive bridges extend betweenthe first and second conductive lines, beginning and ending respectivelyat the first and second conductive lines; wherein the memory devicefurther includes: a third conductive line that extends along the thirdcolumn and is electrically coupled to bit cells of the array in thethird column; and a plurality of second conductive bridges extendingbetween the second and third conductive lines, beginning and endingrespectively at the second and third conductive lines, wherein theconductive bridges and the second conductive bridges are spaced fromeach other and alternate along the second conductive line. In someembodiments, the bit cells of the array are 2T1R RRAM cells. In someembodiments, the bit cells of the array are 1T1R RRAM cells.

In some embodiments, the present application provides a method forforming a memory device, the method including: forming an array ofaccess devices on a substrate, wherein the array of access devicesincludes a plurality of rows and a plurality of columns, and wherein thecolumns are grouped into pairs of neighboring columns; forming aplurality of wires over the array of access devices, wherein theplurality of wires includes: a plurality of source lines including afirst source line and a second source line, wherein each of the sourcelines is individual to one of the pairs of neighboring columns and iselectrically coupled to access devices of the array in the individualpair of neighboring columns; and a plurality of bridges extendingbetween the first and second source lines and electrically coupling thefirst and second source lines together; and forming an array of memorystructures over the plurality of wires, wherein the memory structureselectrically couple to the access devices, respectively, through thewires. In some embodiments, the wires have a common elevation above thesubstrate, and wherein the first source line, the second source line,and the plurality of bridges are integrated together. In someembodiments, the forming of the plurality of wires includes: depositinga dielectric layer over the access devices; patterning the dielectriclayer to form openings having a layout of the wires; depositing aconductive layer filling the openings and covering the dielectric layer;and performing a planarization into the conductive layer until thedielectric layer is reached. In some embodiments, the first and secondsource lines neighbor without intervening source lines. In someembodiments, the bridges are formed with line-shaped top layouts thatbegin and end respectively at the first and second source lines. In someembodiments, the method further includes: forming a plurality of secondwires over the array of memory structures, wherein the plurality ofsecond wires includes a bit line between the first and second sourcelines, and wherein the bit line is individual to one of the columns andis electrically coupled to memory structures overlying the individualcolumn.

In some embodiments, the present application provides another memorydevice including: an array of bit cells, wherein the array includes aplurality of rows and a plurality of columns, and wherein the pluralityof columns includes a first pair of neighboring columns and a secondpair of neighboring columns; and a conductive structure electricallycoupled to bit cells of the array in the first and second pairs ofneighboring columns, wherein the conductive structure has aladder-shaped top layout in which legs of the ladder-shaped top layoutare elongated respectively along the first and second pairs ofneighboring columns. In some embodiments, the bit cells of the arrayinclude individual access transistors, wherein the conductive structureelectrically couples to first source/drain regions of access transistorsin each column of the first and second pairs of neighboring columns. Insome embodiments, the bit cells of the array include individual memorystructures, wherein the memory structures respectively overlie andelectrically couple to second source/drain regions of the accesstransistors. In some embodiments, rungs of the ladder-shaped top layouthave a two-row pitch and are elongated transverse to the columns of thearray. In some embodiments, the plurality of columns includes a thirdpair of neighboring columns, and wherein the first and second pairs ofneighboring columns are separated by the third pair of neighboringcolumns.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method for forming a memory device, the methodcomprising: forming an array of access devices on a substrate, whereinthe array of access devices comprises a plurality of rows, a first pairof columns, and a second pair of columns; forming an interconnectstructure over the array of access devices, wherein the interconnectstructure comprises a plurality of wires and defines a first source lineand a second source line, and wherein the first and second source linesare electrically coupled to access devices of the array respectively inthe first and second pairs of columns; depositing a dielectric layerover the array of access devices; patterning the dielectric layer toform a plurality of openings elongated along the rows; filling theopenings with a conductive material to form a plurality of bridges inthe openings, wherein the bridges at least partially define conductivepaths electrically coupling the first source line to the second sourceline; and forming an array of memory structures over the interconnectstructure and the plurality of bridges, wherein the memory structuresare respectively and electrically coupled to the access devices throughthe interconnect structure.
 2. The method according to claim 1, whereinthe first and second source lines and the bridges have a commonelevation above the substrate and are integrated together.
 3. The methodaccording to claim 1, wherein the filling comprises: depositing theconductive material filling the openings and covering the dielectriclayer; and performing a planarization into the conductive material untilthe dielectric layer is reached.
 4. The method according to claim 1,wherein the first and second source lines neighbor without interveningsource lines.
 5. The method according to claim 1, wherein the openingshave line-shaped top layouts that begin and end respectively anddirectly over the first pair of columns and the second pair of columns.6. The method according to claim 1, further comprising: forming aplurality of additional wires over the array of memory structures,wherein the plurality of additional wires comprises a bit line wirelaterally between the first and second source lines, and wherein the bitline wire is individual to a column in the array of access devices andis electrically coupled to memory structures overlying the column. 7.The method according to claim 1, wherein the patterning defines a pairof additional openings simultaneously with the plurality of openings,wherein the additional openings are elongated respectively along thefirst pair of columns and the second pair of columns, wherein theopenings are between and connect to the additional openings, and whereinthe first and second source lines are formed respectively in theadditional openings.
 8. A method comprising: forming an array oftransistors overlying a substrate, wherein the array comprises aplurality of rows, a first column, and a second column; depositing afirst dielectric layer covering the array; forming a plurality of firstconductive features within the first dielectric layer and electricallycoupled to the transistors; depositing a second dielectric layercovering the first conductive features; performing an etch selectivelyinto the second dielectric layer to form a first trench and a secondtrench elongated respectively along the first and second columns,wherein the first and second trenches partially expose at least some ofthe first conductive features; filling the first and second trencheswith a conductive material to form a first wire and a second wirerespectively in the first and second trenches; and electrically couplingthe first wire to the second wire.
 9. The method according to claim 8,wherein the plurality of first conductive features comprises contactvias extending from a top surface of the first dielectric layerrespectively to the transistors.
 10. The method according to claim 8,wherein the first and second wires electrically couple to source/drainregions of the transistors through the first conductive features. 11.The method according to claim 8, wherein the etch further defines athird trench extending from the first trench to the second trench, andwherein the method further comprises: filling the third trench with theconductive material while filling the first and second trenches with theconductive material to define a conductive bridge electrically couplingthe first wire to the second wire.
 12. The method according to claim 8,wherein the filling comprises: depositing the conductive material in thefirst and second trenches and covering the second dielectric layer; andremoving the conductive material from atop the second dielectric layer.13. The method according to claim 8, wherein the method furthercomprises: forming an array of memory structures overlying the first andsecond wires.
 14. The method according to claim 8, wherein the first andsecond trenches correspond to legs of a ladder-shaped openings formed inthe second dielectric layer by the etch.
 15. A method comprising:forming an array of transistors overlying a substrate, wherein the arraycomprises a plurality of rows, a first column, and a second column;depositing a first dielectric layer covering the array while forming aplurality of first metal features and a plurality of second metalfeatures, wherein the first and second metal features are embedded inthe first dielectric layer and electrically coupled to transistors ofthe array respectively in the first and second columns; patterning thefirst dielectric layer to form an opening, wherein the opening has afirst column segment and a second column segment extending respectivelyalong the first and second columns, from one side of the array to anopposite side of the array, and respectively exposing at least some ofthe first and second metal features, and wherein the opening further hasa bridge segment connecting the first column segment to the secondcolumn segment; depositing a metal layer filling the opening andcovering the first dielectric layer; and performing a planarization intothe metal layer to remove the metal layer from atop the first dielectriclayer.
 16. The method according to claim 15, wherein first and secondmetal features exposed in the opening include contact vias extending tothe substrate.
 17. The method according to claim 15, wherein the bridgesegment of the opening begins and ends respectively and directly overthe first and second columns.
 18. The method according to claim 15,wherein the patterning is performed by a photolithography/etchingprocess.
 19. The method according to claim 15, wherein the patterningforms an additional opening at a common elevation above the substrate asthe opening, wherein the opening extends in a closed path around theadditional opening, wherein the metal layer is deposited filling theadditional opening, and wherein the method further comprises: forming amemory structure directly over and electrically coupled to a portion ofthe metal layer in the additional opening after the planarization. 20.The method according to claim 15, further comprising: forming a trenchisolation structure (TIS) in the substrate, wherein the TIS has a firstline-shaped segment, a second line-shaped segment, and a thirdline-shaped segment that are elongated in parallel along the first andsecond columns, wherein transistors of the array in the first column arebetween and border the first and second line-shaped segments of the TIS,wherein transistors of the array in the second column are between andborder the second and third line-shaped segments of the TIS, and whereinthe first and second column segments of the opening respectively overliethe first and third line-shaped segments of the TIS.